Clock input buffers are used in a number of applications today. Typically, these clock input buffers have a relatively high gain and drive relatively high capacitance loads, and these clock input buffers, oftentimes, have to contend with difficult situations, such as jitter. Particularly, with many high performance applications (e.g., analog-to-digital converters or ADCs), the signal-to-noise ratio or SNR at very high input frequencies is dominated by clock jitter. For these applications, the clock input to the device can be externally filtered by an extremely narrow bandpass filter that effectively reduces the clock jitter. Application of the narrow bandpass filter, though, typically results in a sine wave-like input (i.e., slow edge rates) to the clock input buffers. To compensate for these sine wave-like inputs, the clock input buffer uses the relatively high gain to “square-up” the input clock edges to reduce the affects of internal noise sources, reduce any accumulation of offset errors, and to generally provide a well-defined clock edge for timing sensitive circuits. This combination of high gain and ability to drive a load capacitance results in a circuit that consumes high power.
There are numerous conventional designs for clock input buffers. Some examples are U.S. Pat. Nos. 5,939,942; 6,650,163; 7,345,528; and 7,126,403; U.S. Patent Pre-Grant Publ. No. 2006/0091969; and Razzagh et al. “A 10-b, 1-GSample/s Track-and-Hold Amplifier Using SiGe BiCMOS Technology,” IEEE Custom Integrated Circuits Conference, 2003.
The best known design, though, is U.S. Pat. No. 7,345,528 by Zanchi et al. (“Zanchi”). In particular, Zanchi employs clamps and complementary differential pairs, but Zanchi draws a static current. As a result of this configuration, the current is generally high enough to have a very high slew rate, causing higher power consumption especially when the inputs are not toggling.
Therefore, there is a need for a clock buffer with better performance characteristics.